MIPS architecture

MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Computer Systems (now MIPS Technologies). The early MIPS architectures were 32-bit, and later versions were 64-bit. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations).^[1][2] MIPS32 and MIPS64 define a control register set as well as the instruction set.

Several optional extensions are also available, including MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks,^[3] MDMX (MaDMaX) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room,^[4] and MIPS MT, which adds multithreading capability.^[5]

Computer architecture courses in universities and technical schools often study the MIPS architecture.^[6] The architecture greatly influenced later RISC architectures such as Alpha.

MIPS implementations are currently primarily used in many embedded systems such as Windows CE devices, routers, residential gateways, and video game consoles such as the Sony PlayStation 2 and PlayStation Portable. Until late 2006, they were also used in many of SGI's computer products. MIPS implementations were also used by Digital Equipment Corporation, NEC, Pyramid Technology, Siemens Nixdorf, Tandem Computers and others during the late 1980s and 1990s. In the mid to late 1990s, it was estimated that one in three RISC microprocessors produced were MIPS implementations.

History

RISC pioneer

In 1981, a team led by John L. Hennessy at Stanford University started work on what would become the first MIPS processor. The basic concept was to increase performance through the use of deep instruction pipelines. Pipelining as a basic technique was well known before (see IBM 801 for instance), but not developed into its full potential. CPUs are built up from a number of dedicated sub-units such as instruction decoders, ALUs (integer arithmetics and logic), load/store units (handling memory), and so on. In a traditional non-optimized design, a particular instruction in a program sequence must be (almost) completed before the next can be issued for execution; in a pipelined architecture, successive instructions can instead overlap in execution. For instance, at the same time a math instruction is fed into the floating point unit, the load/store unit can fetch the next instruction.

One major barrier to pipelining was that some instructions, like division, take longer to complete and the CPU therefore has to wait before passing the next instruction into the pipeline. One solution to this problem is to use a series of interlocks that allows stages to indicate that they are busy, pausing the other stages upstream. Hennessy's team viewed these interlocks as a major performance barrier since they had to communicate to all the modules in the CPU which takes time, and appeared to limit the clock speed. A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

Although this design eliminated a number of useful instructions such as multiply and divide it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate. The elimination of these instructions became a contentious point.

The other difference between the MIPS design and the competing Berkeley RISC involved the handling of subroutine calls. RISC used a technique called register windows to improve performance of these very common tasks, but this limited the maximum depth of multi-level calls. Each subroutine call required its own set of registers, which in turn required more real estate on the CPU and more complexity in its design. Hennessy felt that a careful compiler could find free registers without resorting to a hardware implementation, and that simply increasing the number of registers would not only make this simple, but increase the performance of all tasks.

In other ways the MIPS design was very much a typical RISC design. To save bits in the instruction word, RISC designs reduce the number of instructions to encode. The MIPS design uses 6 bits of the 32-bit word for the basic opcode;^[7] the rest may contain a single 26-bit jump address or it may have up to four 5-bit fields specifying up to three registers plus a shift value combined with another 6-bits of opcode; another format, among several, specifies two registers combined with a 16-bit immediate value, etc. This allowed this CPU to load up the instruction and the data it needed in a single cycle, whereas an (older) non-RISC design, such as the MOS Technology 6502 for instance, required separate cycles to load the opcode and the data. This was one of the major performance improvements that RISC offered. However, modern non-RISC designs achieve this speed by other means (such as queues in the CPU).

First hardware

In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the R2000, in 1985, improving the design as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in SGI's series of workstations. These commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others).

In 1991 MIPS released the first 64-bit microprocessor, the R4000. The R4000 has an advanced TLB where the entry contains not just virtual address but also the virtual address space id. Such buffer eliminates the major performance problems from microkernels^[8] that are slow on competing architectures (Pentium, PowerPC, Alpha) because of the need to flush the TLB on the frequent context switches. However, MIPS had financial difficulties while bringing it to market. The design was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost. As a subsidiary of SGI, the company became known as MIPS Technologies

Licensable architecture

In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count and price—the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins. Sun Microsystems attempted to enjoy similar success by licensing their SPARC core but was not nearly as successful. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous 68k family. MIPS was so successful that SGI spun off MIPS Technologies in 1998. Fully half of MIPS' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.

In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 (based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V) and the 64-bit MIPS64 (based on MIPS V). NEC, Toshiba and SiByte (later acquired by Broadcom) each obtained licenses for the MIPS64 as soon as it was announced. Philips, LSI Logic and IDT have since joined them. Success followed success, and today the MIPS cores are one of the most-used "heavyweight" cores in the marketplace for computer-like devices (hand-held computers, set-top boxes, etc.), with other designers fighting it out for other niches.

Since the MIPS architecture is licensable, it has attracted several processor start-up companies over the years. One of the first start-ups to design MIPS processors was Quantum Effect Devices (see next section). The MIPS design team that designed the R4300i started the company SandCraft, which designed the R5432 for NEC and later produced the SR71000, one of the first out-of-order execution processors for the embedded market. The original DEC StrongARM team eventually split into two MIPS-based start-ups: SiByte which produced the SB-1250, one of the first high-performance MIPS-based systems-on-a-chip (SOC); while Alchemy Semiconductor (later acquired by AMD) produced the Au-1000 SoC for low-power applications. Lexra used a MIPS-like architecture and added DSP extensions for the audio chip market and multithreading support for the networking market. Due to Lexra not licensing the architecture, two lawsuits were started between the two companies. The first was quickly resolved when Lexra promised not to advertise their processors as MIPS-compatible. The second (about MIPS patent 4814976 for handling unaligned memory access) was protracted, hurt both companies' business, and culminated in MIPS Technologies giving Lexra a free license and a large cash payment.

Two companies have emerged that specialize in building multi-core devices using the MIPS architecture. Raza Microelectronics, Inc. purchased the product line from failing SandCraft and later produced devices that contained eight cores that were targeted at the telecommunications and networking markets. Cavium Networks, originally a security processor vendor also produced devices with eight CPU cores, and later up to 32 cores, for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.

Losing the desktop

Among the manufacturers which have made computer workstation systems using MIPS processors are SGI, MIPS Computer Systems, Inc., Whitechapel Workstations, Olivetti, Siemens-Nixdorf, Acer, Digital Equipment Corporation, NEC, and DeskStation. Operating systems ported to the architecture include SGI's IRIX, Microsoft's Windows NT (until v4.0), Windows CE, Linux, BSD, UNIX System V, SINIX, QNX, and MIPS Computer Systems' own RISC/os.

There was speculation in the early 1990s that MIPS and other powerful RISC processors would overtake the Intel IA32 architecture. This was encouraged by the support of the first two versions of Microsoft's Windows NT for Alpha, MIPS and PowerPC - and to a lesser extent the Clipper architecture and SPARC. However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4.0 dropped support for anything but Intel and Alpha. With SGI's decision to transition to the Itanium and IA32 architectures, use of MIPS processors on the desktop has now disappeared almost completely.^[9]

Embedded markets

The Ingenic JZ4730 is an example for a MIPS based SoC

Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking, telecommunications, video arcade games, video game consoles, computer printers, digital set-top boxes, digital televisions, DSL and cable modems, and personal digital assistants.

The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.

Synthesizeable cores for embedded markets

In recent years most of the technology used in the various MIPS generations has been offered as IP-cores (building-blocks) for embedded processor designs. Both 32-bit and 64-bit basic cores are offered, known as the 4K and 5K. These cores can be mixed with add-in units such as FPUs, SIMD systems, various input/output devices, etc.

MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer Cisco, Linksys and Mikrotik's routerboard routers, cable modems and ADSL modems, smartcards, laser printer engines, set-top boxes, robots, handheld computers, Sony PlayStation 2 and Sony PlayStation Portable. In cellphone/PDA applications, MIPS has been largely unable to displace the incumbent, competing ARM architecture.

MIPS architecture processors include: IDT RC32438; ATI Xilleon; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; Microchip Technology PIC32; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500; Oak Technologies Generation; PMC-Sierra RM11200; QuickLogic QuickMIPS ESP; Toshiba Donau, Toshiba TMPR492x, TX4925, TX9956, TX7901.

MIPS-based supercomputers

One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers. Silicon Graphics (SGI) refocused its business from desktop graphics workstations to the high performance computing (HPC) market in the early 1990s. The success of the company's first foray into server systems, the Challenge series based on the R4400 and R8000, and later R10000, motivated SGI to create a vastly more powerful system. The introduction of the integrated R10000 allowed SGI to produce a system, the Origin 2000, eventually scalable to 1024 CPUs using its NUMAlink cc-NUMA interconnect. The Origin 2000 begat the Origin 3000 series which topped out with the same 1024 maximum CPU count but using the R14000 and R16000 chips up to 700 MHz. Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.

An HPC startup called SiCortex, Inc. introduced a massively parallel MIPS based supercomputer in 2007. The machines are based on the MIPS64 architecture and a high performance interconnect using a Kautz graph topology. The system is very power efficient and computationally powerful. The most unique aspect of the system is its multicore processing node which integrates six MIPS64 cores, a crossbar memory controller, interconnect DMA engine, Gigabit Ethernet and PCI Express controllers all on a single chip which consumes only 10 watts of power, yet has a peak floating point performance of 6 GFLOPs. The most powerful configuration, the SC5832, is a single cabinet supercomputer consisting of 972 such node chips for a total of 5832 MIPS64 processor cores and 8.2 teraFLOPS of peak performance.

Returning to Desktop by Loongson

Loongson, which was designed in the hope of circumventing the MIPS patent, released its desktop version supported by Linux. As Loongson could be made more cheaply, the renaissance of MIPS in the desktop market, especially in the low-end market, is possible.

MIPS architecture processors are also used in netbooks sold by iUnika, Bestlink, and Golden Delicious Computers.^[10][11]

MIPS IV

MIPS IV is the fourth version of the architecture. It is a superset of MIPS III and is compatible with all existing versions of MIPS. The first implementation of MIPS IV was the R8000, which was introduced in 1994. MIPS IV added:

• Register + register addressing for floating point loads and stores
• Single- and double-precision floating point fused-multiply adds and subtracts
• Conditional move instructions for both integer and floating-point
• Extra condition bits in the floating point control and status register, bringing the total to eight

MIPS V

MIPS V is the fifth version of the architecture, announced on 21 October 1996 at the Microprocessor Forum 1996.^[12] MIPS V was designed to improve the performance of 3D graphics applications. In the mid-1990s, a major use of non-embedded MIPS microprocessors were graphics workstations from SGI. MIPS V was complemented by the integer-only MIPS Digital Media Extensions (MDMX) multimedia extensions, which were announced on the same date as MIPS V.^[13]

MIPS V implementations were never introduced. In 1997, SGI announced the "H1" or "Beast" and the "H2" or "Capitan" microprocessors. The former was to have been the first MIPS V implementation, and was due to be introduced in 1999. The "H1" and "H2" projects were later combined and were eventually canceled in 1998.

MIPS V added a new data type, the pair-single (PS), which consisted of two single-precision (32-bit) floating-point numbers stored in the existing 64-bit floating-point registers. Variants of existing floating-point instructions for arithmetic, compare and conditional move were added to operate on this data type in a SIMD fashion. New instructions were added for loading, rearranging and converting PS data. It was the first architecture to exploit floating-point SIMD with existing resources.^[13]

CPU family

Pipelined MIPS, showing the five stages (instruction fetch, instruction decode, execute, memory access and write back)

The first commercial MIPS model, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the register file; these result-retrieving instructions were interlocked.

The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the Alpha. Unlike other registers, the program counter is not directly accessible.

The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.

The R3000 succeeded the R2000 in 1988, adding 32 KB (soon increased to 64 KB) caches for instructions and data, along with cache coherency support for multiprocessor use. While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in MMU, a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a R3010 FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the R3000A delivered a performance of 32 VUPs (VAX Unit of Performance). The MIPS R3000A-compatible R3051 running at 33.8688 MHz was the processor used in the Sony PlayStation. Third-party designs include Performance Semiconductor's R3400 and IDT's R3500, both of them were R3000As with an integrated R3010 FPU. Toshiba's R3900 was a virtually first SoC for the early handheld PCs that ran Windows CE. A radiation-hardened variant for space applications, the Mongoose-V, is a R3000 with an integrated R3010 FPU.

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and they took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). The improved R4400 followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache.

MIPS, now a division of SGI called MTI, designed the low-cost R4200, the basis for the even cheaper R4300i. A derivative of this microprocessor, the NEC VR4300, was used in the Nintendo 64 game console.^[14]

bottom-side view of package of R4700 Orion with the exposed silicon chip, fabricated by IDT, designed by Quantum Effect Devices

topside view of package for R4700 Orion

Quantum Effect Devices (QED), a separate company started by former MIPS employees, designed the R4600 Orion, the R4700 Orion, the R4650 and the R5000. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. The RM7000 included an on-board 256 KB level 2 cache and a controller for optional level three cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller, PCI controller, gigabit ethernet controller and fast IO such as a hypertransport port.

The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER Challenge servers in the mid 1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.

In 1995, the R10000 was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

Later designs have all been based upon R10000 core. The R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised R14000 allowed higher clock rates with additional support for DDR SRAM in the off-chip cache. Later iterations are named the R16000 and the R16000A and feature increased clock speed, additional L1 cache, and smaller die manufacturing compared with before.

Other members of the MIPS family include the R6000, an ECL implementation produced by Bipolar Integrated Technology. The R6000 introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market.

MIPS I instruction formats

Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.^[15][16]

The following are the three formats used for the core instruction set:

MIPS assembly language

These are assembly language instructions that have direct hardware implementation, as opposed to pseudoinstructions which are translated into multiple real instructions before being assembled.

• In the following, the register letters d, t, and s are placeholders for (register) numbers or register names.
• C denotes a constant (immediate).
• All the following instructions are native instructions.
• Opcodes and funct codes are in hexadecimal.
• The MIPS32 Instruction Set states that the word unsigned as part of Add and Subtract instructions, is a misnomer. The difference between signed and unsigned versions of commands is not a sign extension (or lack thereof) of the operands, but controls whether a trap is executed on overflow (e.g. Add) or an overflow is ignored (Add unsigned). An immediate operand CONST to these instructions is always sign-extended.

Integer

MIPS has 32 integer registers. Data must be in registers to perform arithmetic. Register $0 always holds 0 and register $1 is normally reserved for the assembler (for handling pseudo instructions and large constants).

The encoding shows which bits correspond to which parts of the instruction. A hyphen (-) is used to indicate don't cares.

Category	Name	Instruction syntax	Meaning	Format/opcode/funct			Notes/Encoding
Arithmetic	Add	add $d,$s,$t	$d = $s + $t	R	0	2016	adds two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100000
	Add unsigned	addu $d,$s,$t	$d = $s + $t	R	0	2116	as above but ignores an overflow 000000ss sssttttt ddddd--- --100001
	Subtract	sub $d,$s,$t	$d = $s - $t	R	0	2216	subtracts two registers, executes a trap on overflow 000000ss sssttttt ddddd--- --100010
	Subtract unsigned	subu $d,$s,$t	$d = $s - $t	R	0	2316	as above but ignores an overflow 000000ss sssttttt ddddd000 00100011
	Add immediate	addi $t,$s,C	$t = $s + C (signed)	I	816	-	Used to add sign-extended constants (and also to copy one register to another: addi $1, $2, 0), executes a trap on overflow 001000ss sssttttt CCCCCCCC CCCCCCCC
	Add immediate unsigned	addiu $t,$s,C	$t = $s + C (signed)	I	916	-	as above but ignores an overflow, C still sign-extended 001001ss sssttttt CCCCCCCC CCCCCCCC
	Multiply	mult $s,$t	LO = (($s * $t) << 32) >> 32; HI = ($s * $t) >> 32;	R	0	1816	Multiplies two registers and puts the 64-bit result in two special memory spots - LO and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) $s * $t . See mfhi and mflo for accessing LO and HI regs.
	Divide	div $s, $t	LO = $s / $t     HI = $s % $t	R	0	1A16	Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.[15]
	Divide unsigned	divu $s, $t	LO = $s / $t     HI = $s % $t	R	0	1B16	Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.
Data Transfer	Load double word	ld $t,C($s)	$t = Memory[$s + C]	I	2316	-	loads the word stored from: MEM[$s+C] and the following 7 bytes to $t and the next register.
	Load word	lw $t,C($s)	$t = Memory[$s + C]	I	2316	-	loads the word stored from: MEM[$s+C] and the following 3 bytes.
	Load halfword	lh $t,C($s)	$t = Memory[$s + C] (signed)	I	2116	-	loads the halfword stored from: MEM[$s+C] and the following byte. Sign is extended to width of register.
	Load halfword unsigned	lhu $t,C($s)	$t = Memory[$s + C] (unsigned)	I	2516	-	As above without sign extension.
	Load byte	lb $t,C($s)	$t = Memory[$s + C] (signed)	I	2016	-	loads the byte stored from: MEM[$s+C].
	Load byte unsigned	lbu $t,C($s)	$t = Memory[$s + C] (unsigned)	I	2416	-	As above without sign extension.
	Store double word	sd $t,C($s)	Memory[$s + C] = $t	I		-	stores two words from $t and the next register into: MEM[$s+C] and the following 7 bytes. The order of the operands is a large source of confusion.
	Store word	sw $t,C($s)	Memory[$s + C] = $t	I	2B16	-	stores a word into: MEM[$s+C] and the following 3 bytes. The order of the operands is a large source of confusion.
	Store half	sh $t,C($s)	Memory[$s + C] = $t	I	2916	-	stores the first half of a register (a halfword) into: MEM[$s+C] and the following byte.
	Store byte	sb $t,C($s)	Memory[$s + C] = $t	I	2816	-	stores the first fourth of a register (a byte) into: MEM[$s+C].
	Load upper immediate	lui $t,C	$t = C << 16	I	F16	-	loads a 16-bit immediate operand into the upper 16-bits of the register specified. Maximum value of constant is 216-1
	Move from high	mfhi $d	$d = HI	R	0	1016	Moves a value from HI to a register. Do not use a multiply or a divide instruction within two instructions of mfhi (that action is undefined because of the MIPS pipeline).
	Move from low	mflo $d	$d = LO	R	0	1216	Moves a value from LO to a register. Do not use a multiply or a divide instruction within two instructions of mflo (that action is undefined because of the MIPS pipeline).
	Move from Control Register	mfcZ $t, $s	$t = Coprocessor[Z].ControlRegister[$s]	R	0		Moves a 4 byte value from Coprocessor Z Control register to a general purpose register. Sign extension.
	Move to Control Register	mtcZ $t, $s	Coprocessor[Z].ControlRegister[$s] = $t	R	0		Moves a 4 byte value from a general purpose register to a Coprocessor Z Control register. Sign extension.
Logical	And	and $d,$s,$t	$d = $s & $t	R	0	2416	Bitwise and 000000ss sssttttt ddddd--- --100100
	And immediate	andi $t,$s,C	$t = $s & C	I	C16	-	001100ss sssttttt CCCCCCCC CCCCCCCC
	Or	or $d,$s,$t	$d = $s | $t	R	0	2516	Bitwise or
	Or immediate	ori $t,$s,C	$t = $s | C	I	D16	-
	Exclusive or	xor $d,$s,$t	$d = $s ^ $t	R	0	2616
	Nor	nor $d,$s,$t	$d = ~ ($s | $t)	R	0	2716	Bitwise nor
	Set on less than	slt $d,$s,$t	$d = ($s < $t)	R	0	2A16	Tests if one register is less than another.
	Set on less than immediate	slti $t,$s,C	$t = ($s < C)	I	A16	-	Tests if one register is less than a constant.
Bitwise Shift	Shift left logical	sll $t,$s,C	$t = $s << C	R	0	0	shifts C number of bits to the left (multiplies by )
	Shift right logical	srl $t,$s,C	$t = $s >> C	R	0	216	shifts CONST number of bits to the right - zeros are shifted in (divides by ). Note that this instruction only works as division of a two's complement number if the value is positive.
	Shift right arithmetic	sra $t,$s,C		R	0	316	shifts C number of bits - the sign bit is shifted in (divides 2's complement number by )
Conditional branch	Branch on equal	beq $s,$t,C	if ($s == $t) go to PC+4+4*C	I	416	-	Goes to the instruction at the specified address if two registers are equal. 000100ss sssttttt CCCCCCCC CCCCCCCC
	Branch on not equal	bne $s,$t,C	if ($s != $t) go to PC+4+4*C	I	516	-	Goes to the instruction at the specified address if two registers are not equal.
Unconditional jump	Jump	j C	PC = PC+4[31:28] . C*4	J	216	-	Unconditionally jumps to the instruction at the specified address.
	Jump register	jr $s	goto address $s	R	0	816	Jumps to the address contained in the specified register
	Jump and link	jal C	$31 = PC + 8; PC = PC+4[31:28] . C*4	J	316	-	For procedure call - used to call a subroutine, $31 holds the return address; returning from a subroutine is done by: jr $31. Return address is PC + 8, not PC + 4 due to the use of a branch delay slot which forces the instruction after the jump to be executed

Note: In MIPS assembly code, the offset for branching instructions can be represented by a label elsewhere in the code.

Note: There is no corresponding load lower immediate instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register $0 (whose value is always zero). For example, both addi $1, $0, 100 and ori $1, $0, 100 load the decimal value 100 into register $1.

Note: Subtracting an immediate can be done with adding the negation of that value as the immediate.

Floating point

MIPS has 32 floating-point registers. Two registers are paired for double precision numbers. Odd numbered registers cannot be used for arithmetic or branching, just as part of a double precision register pair.

Pseudo instructions

These instructions are accepted by the MIPS assembler, however they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.

Some other important instructions

• NOP (no operation) (machine code 0x00000000, interpreted by CPU as sll $0,$0,0)
• break (breaks the program, used by debuggers)
• syscall (used for system calls to the operating system)

Compiler register usage

The hardware architecture specifies that:

• General purpose register $0 always returns a value of 0 .
• General purpose register $31 is used as the link register for jump and link instructions.
• HI and LO are used to access the multiplier/divider results, accessed by the mfhi (move from high) and mflo commands.

These are the only hardware restrictions on the usage of the general purpose registers.

The various MIPS tool-chains implement specific calling conventions that further restrict how the registers are used. These calling conventions are totally maintained by the tool-chain software and are not required by the hardware.

Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, $s-registers must be saved to the stack by a procedure that needs to use them, and $sp and $fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, $ra is changed automatically by any normal function call (ones that use jal), and $t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call).

Simulators

Open Virtual Platforms (OVP)^[17] includes the freely available for non-commercial use simulator OVPsim, a library of models of processors, peripherals and platforms, and APIs which enable users to develop their own models. The models in the library are open source, written in C, and include the MIPS 4K, 24K and 34K cores. These models are created and maintained by Imperas^[18] and in partnership with MIPS Technologies have been tested and assigned the MIPS-Verified (tm) mark. Sample MIPS-based platforms include both bare metal environments and platforms for booting unmodified Linux binary images. These platforms–emulators are available as source or binaries and are fast, free, and easy to use. OVPsim is developed and maintained by Imperas and is very fast (hundreds of million of instructions per second), and built to handle multicore architectures.

There is a freely available MIPS32 simulator (earlier versions simulated only the R2000/R3000) called SPIM for use in education. EduMIPS64^[19] is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. It has educational purposes and is used in some computer architecture courses in universities around the world.

MARS^[20] is another GUI-based MIPS emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design.

More advanced free emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects. These emulate the various MIPS III and IV microprocessors in addition to entire computer systems which use them.

Commercial simulators are available especially for the embedded use of MIPS processors, for example Virtutech Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K).

See also

• DLX, a very similar architecture designed by John L. Hennessy (creator of MIPS) for teaching purposes
• MIPS-X, developed as a follow-on project to the MIPS architecture

References

Further reading

• Patterson, David A; John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann Publishers. ISBN 1-55860-604-1. 
• Sweetman, Dominic. See MIPS Run, 2nd edition. Morgan Kaufmann Publishers. ISBN 0-12088-421-6. 
• Sweetman, Dominic. See MIPS Run. Morgan Kaufmann Publishers. ISBN 1-55860-410-3. 
• Farquhar, Erin; Philip Bunce. MIPS Programmer's Handbook. Morgan Kaufmann Publishers. ISBN 1-55860-297-6. 

External links

• MIPS Architectures at MIPS Technologies
• Full overview of MIPS architecture
• Patterson & Hennessy - Appendix A
• Summary of MIPS assembly language
• MIPS Instruction reference
• MARS (MIPS Assembler and Runtime Simulator)
• MIPS processor images and descriptions at cpu-collection.de
• A programmed introduction to MIPS assembly
• Mips bitshift operators
• MIPS software user's manual
• MIPS Architecture history diagram